SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

3.1.2 Updating Source to Set Available Memory Size

In addition to updating the DDRSS registers, other source files in u-boot may need to be updated for the system to operate as expected.

As an example, the total available memory size on a custom board may differ compared to the TI EVM. The default software in the SDK makes use of the u-boot global data and board info structures, specifically the ram_size variable, which should be configured to match the total DDR memory size, and the bi_dram structure's start and size parameters, which map the processor's corresponding address space to the DDR memory region. However, these parameters are not configured based on register settings or output from the Jacinto 7 DDRSS Register Configuration Tool. Thus, these variables must be updated to ensure that the system does not try to access unavailable physical memory when the custom board has less memory compared to the EVM, as well as allow the system to utilize the full DDR memory space when the custom board has more memory compared to the EVM.

In the default SDK source code, the ram_size and bi_dram structure variables are configured in functions dram_init and dram_init_banksize, located in the corresponding processor board file. An example is provided below:

Source: board/ti/j721e/evm.c

As shown below, the function dram_init configures the global data variable ram_size. This function should be modified in custom code and ram_size should be configured to match the total available DDR memory.

int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
	gd->ram_size = 0x100000000;
#else
	gd->ram_size = 0x80000000;
#endif

	return 0;
}

As shown below, the function dram_init_banksize configures the global data variables ram_size and board info bi_dram. This function should be modified in custom code. The variable ram_size should be configured to match the total available DDR memory. The start and size parameters of the bi_dram structure should be configured to match the available memory for each DDR section. For Jacinto 7 processors, the DDR memory is split into a low and high region. The low region is 32-bit addressable, but limited to 2GB. In the example below, 4GB is split across the low and high region such that each region is mapped to 2GB.


int dram_init_banksize(void)
{
	/* Bank 0 declares the memory available in the DDR low region */
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = 0x80000000;
	gd->ram_size = 0x80000000;

#ifdef CONFIG_PHYS_64BIT
	/* Bank 1 declares the memory available in the DDR high region */
	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
	gd->bd->bi_dram[1].size = 0x80000000;
	gd->ram_size = 0x100000000;
#endif

	return 0;
}