SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

2.1.2 Memory Burst Configuration

Additional details of each parameter of this section can be found in the list below:

  1. Burst Length:
    1. Description: This parameter corresponds to MR1[1:0] of the LPDDR4 memory and defines the number of data bits transferred on each data pin during a single READ or WRITE command.
    2. Valid Values: Defined by a drop-down menu list, matching the supported burst length by the tool. Although additional configurations may be supported by the LPDDR4 memory, only 16-bit sequential burst length is supported by the tool.
  2. Read Preamble:
    1. Description: This parameter corresponds to MR1[3] of the LPDDR4 memory and defines whether the READ preamble toggles.
    2. Valid Values: Defined by a drop-down menu list.
  3. Read Postamble:
    1. Description: This parameter corresponds to MR1[7] of the LPDDR4 memory and defines the length of the READ postamble in clock cycles.
    2. Valid Values: Defined by a drop-down menu list.
  4. Write Postamble:
    1. Description: This parameter corresponds to MR3[1] of the LPDDR4 memory and defines the length of the WRITE postamble in clock cycles.
    2. Valid Values: Defined by a drop-down menu list.
  5. Data Bus Inversion (Read):
    1. Description: This parameter corresponds to MR3[6] of the LPDDR4 memory and defines whether the data bus inversion (DBI) function is enabled during READs.
    2. Valid Values: Defined by a drop-down menu list.
  6. Data Bus Inversion (Write):
    1. Description: This parameter corresponds to MR3[7] of the LPDDR4 memory and defines whether the data bus inversion (DBI) function is enabled during WRITEs.
    2. Valid Values: Defined by a drop-down menu list.