SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The main constraint in determining layer count is the number of layers required to implement the high-speed DDR4 / LPDDR4 interface. Memory layout meeting the recommended guidelines typically requires the number of layers used in the Starter Kit (TI recommended). Optimization of layer count could be possible based on the board design and functionalities. Refer to package specific (ALW or AMC) Escape Routing for PCB Design guide. Use of TI Via Channel Array (VCA) technology with the ALW package supports further layer optimization.
Refer the AM62x and AM62Ax DDR Board Design and Layout Guidelines available on TI.com for further guidance and best practices in implementing the DDR4 / LPDDR4 interface.