SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Refer to AM62x DDR Board Design and Layout Guidelines. The goal of the guide is to simplify the DDR4 or LPDDR4 implementation. Requirements have been captured as a set of layout (placement and routing) guidelines that allow board designers to successfully implement a robust design for the topologies supported by the processor. Any follow-up design support that may be required will be provided only for board designs using DDR4 or LPDDR4 memories that follow the guidelines.
The target impedance is 40 Ω (single-ended) and 80 Ω (differential) for the DDR4 or LPDDR4 signals.
For the propagation delay, the delay to be considered for DDR4 or LPDDR4 is the delay related to the traces on the board.
In-case package level propagation delay is required, reach-out to the local TI sales representative.
Refer AM62x DDR Board Design and Layout Guidelines for DDR4 data rate, device bit width, device count and LPDDR4 Count, Channel Width, Channels, Die, Ranks. Guidelines for bit swapping is also included.
It is highly recommended to perform signal integrity simulations during board schematics design and layout stage.