SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The CPSW3G interface can be configured either as a 3-port switch (interfaces to two external Ethernet ports (port 1 and 2)) or a dual independent MAC interface having their own MAC address.
CPSW3G supports RMII (10/100) or RGMII (10/100/1000) interface for each of the external Ethernet interface port.
For RMII interface implementation, refer the CPSW0 RMII Interface section of the device-specific TRM.
CPSW3G interfaces to EPHY configured for different configurations - external 50 MHz (Buffered External Oscillator or processor clock out) as EPHY clock input or 25 MHz EPHY clock input with 50 MHz clock output from EPHY.
One of the CPSW3G port is an internal CPPI (Communications Port Programming Interface) host port. It is a streaming interface to provide data from DMA to CPSW3G and vice-versa.
CPSW3G allows using mixed RGMII/RMII interface topology for the 2 X external interface ports.
RGMII_ID (internal delay) is not timed, tested, or characterized. RGMII_ID is enabled by default and the register bit is reserved.
For more details on the CPSW3G Ethernet interface, refer the High-speed Serial Interfaces section in the Peripherals chapter of the device-specific TRM.