SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
DDR Subsystem supports LPDDR4 or DDR4 memory interface. Refer Memory Subsystem, DDR Subsystem (DDRSS) section in the Features chapter of device-specific data sheet for data bus width, inline ECC support, speed and max addressable range selection.
The allowed memory configurations are 1 X 16-bit or 2 X 8-bit.
1 X 8-bit memory configuration is not a valid configuration.
Based on the application requirements, same memory (LPDDR4) device can be used with the AM625 / AM623 / AM625-Q1 / AM620-Q1 and AM62A7 / AM62A3 processors due to the availability of 1 X 16-bit configuration.
Refer Pin Connectivity Requirements section of the device-specific data sheet for connecting the DDRSS signals when not used.
For more details, refer the DDR Subsystem (DDRSS) section in the Memory Controllers chapter of the device-specific TRM.