SPRAD61A March   2023  – November 2023 AM2732 , AM2732 , AM2732-Q1 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 QSPI Memory Controller Implementation
    3. 5.3 ROM QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Layer Stackup
    1. 9.1 TMDS273GPEVM Layer Stackup
      1. 9.1.1 TMDS273GPEVM Key Stackup Features
    2. 9.2 Four Layer ZCE Example Layer Stackup
      1. 9.2.1 ZCE Four Layer Example Key Stackup Features
    3. 9.3 Four Layer NZN Example Layer Stackup
      1. 9.3.1 NZN Four Layer Example Key Stackup Features
  13. 10Vias
  14. 11BGA Power Fan-Out and Decoupling Placement
    1. 11.1 Ground Return
      1. 11.1.1 Ground Return - TMDS273GPEVM
      2. 11.1.2 Ground Return - ZCE Four Layer Example
      3. 11.1.3 Ground Return - NZN Four Layer Example
    2. 11.2 1.2 V Core Digital Power
      1. 11.2.1 1.2 V Core Digital Power Key Layout Considerations
        1. 11.2.1.1 1.2V Core Layout - TMDS273GPEVM
        2. 11.2.1.2 1.2V Core Layout - ZCE Four Layer Example
        3. 11.2.1.3 1.2V Core Layout - NZN Four Layer Example
    3. 11.3 3.3 V Digital and Analog Power
      1. 11.3.1 3.3 V Digital and Analog Power Key Layout Considerations
        1. 11.3.1.1 3.3V Digital and Analog Layout - TMDS273GPEVM
        2. 11.3.1.2 3.3V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.3.1.3 3.3V Digital and Analog Layout - NZN Four Layer Example
    4. 11.4 1.8 V Digital and Analog Power
      1. 11.4.1 1.8 V Digital and Analog Power Key Layout Considerations
        1. 11.4.1.1 1.8V Digital and Analog Layout - TMDS273GPEVM
        2. 11.4.1.2 1.8V Digital and Analog Layout - ZCE Four Layer Example
        3. 11.4.1.3 1.8V Digital and Analog Layout - NZN Four Layer Example
  15. 12References
  16. 13Revision History

4 Resets

The AM273x MCU has two hardware reset sources:

  • NRESET: Power on reset (logic low enable) signal, ZCE pin L2, NZN pin J3
    • The power-on default configuration sets this pin as an LVCMOS, Failsafe, open-drain output.
    • Should be driven from the power-good circuits of the associated 1.2 V core and 3.3 V I/O regulators or PMIC Reset Out output
  • WARM_RESET: Warm reset input and reset status output signal, ZCE pin K1, NZN pin H3
    • The power-on default configuration sets this pin as an LVCMOS open-drain output with the internal pull status disabled
    • When the device enters reset, this signal is driven logic low.
    • When the device is fully out of reset, this signal is driven logic high.

The NRESET is intended to be kept at logic low at initial startup of the system. Once each regulator or PMIC sourcing the AM273x power pins has been verified to be operating at nominal output voltage, then the NRESET signal can be brought up to logic high. This action will start the AM273x boot ROM execution, beginning with sampling of the SOP pins. The AM273x GPEVM implementation does this with the nRSTOUT pin of the LP877451A PMIC. A weak pull-down resistor is recommended on the PORZ signal to keep the signal low before startup of the system. PORz should be forced low if either 1.2 V or 3.3 V rail power goes below the nominal operating range.

For a full description of the power-on and power-off reset sequencing requirements, see the AM273x Sitara™ Microcontroller Data Sheet.

The WARMRSTN pin is a multi-purpose software reset input and hardware reset status pin. In the power-on-default configuration, this pin is configured as an open-drain output and requires an external pull-up resistor to VIOIN 1.8/3.3 V I/O voltage rail. In this mode, WARMRSTN can be used as an MCU reset indicator and can be used to drive reset input for attached peripheral IC such as Ethernet PHY and memories.

WARMRSTN can also be configured by software as software reset. Additional software reset sources are also available on the AM273x devices. For more information on reset functionality, see the Reset chapter in the AM273x Sitara™ Microcontroller Technical Reference Manual.

Because of the default open-drain configuration of this pin, if both the reset status output mode and the software reset input mode are needed in a design, it is recommended that open-drain buffers be used to drive the optional reset input status.