SPRADP5 January   2026 AM62P , AM62P

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stack-Up
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References

3.1 Board Model Extraction

The board level extraction guidelines listed below are intended to work in any EDA extraction tool and are not tool-specific. It is important to follow the steps outlined in Section 3.2 immediately after completing touchstone model extractions. The design must be checked with these steps prior to running IBIS simulations.

  1. For Power extractions, always extract power in a 3D-EM solver.
  2. For signal extractions, a 2.5D extraction is sufficient
  3. Use wide-band models. TI recommends to extract from DC to at least until 6x the Nyquist frequency (for example, for eMMC HS400 extract the model at least until 2.4GHz).
  4. Check the board stack-up for accurate layer thickness and material properties.
    1. TI recommends to use Djordjevic-Sarkar models for the dielectric material definition.
  5. Use accurate etch profiles and surface roughness for the signal traces across all layers in the stack-up.
  6. If the board layout is cut prior to extraction (to reduce simulation time), then define a cut boundary that is at least 0.25 inch away from the signal and power nets.
  7. Check the via pad stack definitions.
    1. Make sure that the non-functional internal layer pads on signal vias are modeled the same way the pads are fabricated.
    2. These non-functional internal layer pads on signal vias are not recommended by TI.
  8. Use Spice/S-parameter models (typically available from the vendor) for modeling all passives in the system.