SPRADP5 January   2026 AM62P , AM62P

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stack-Up
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References

1.2 General Board Layout Guidelines

To verify good signaling performance, the following general board design guidelines must be followed:

  • Always follow the TI example layouts and EVM designs as close as possible. If concepts or routing strategies are not understood, then ask questions on E2E.
  • All signals need ground reference (strongly suggest on both sides).
  • Avoid crossing plane splits in the signal reference planes.
  • Use the widest trace that is practical between decoupling capacitors and supply pin.
  • Minimize inter-symbol interference (ISI) by keeping impedance matched.
  • Minimize crosstalk by isolating sensitive signals, such as strobes and clocks, and by using a proper PCB stack-up.
  • Avoid return path discontinuities by adding vias or capacitors whenever signals change layers and reference planes.
  • Minimize reference voltage noise through proper isolation and proper use of decoupling capacitors.
  • Keep the signal routing stub lengths as short as possible.
  • Add additional spacing for clock and strobe nets to minimize crosstalk.
  • Maintain a common ground (also called GND) reference for all signals and for all bypass and decoupling capacitors.
  • Consider the differences in propagation delays between microstrip and stripline nets when evaluating timing constraints.
  • via-to-via coupling can be significant part of PCB-level crosstalk. Dimension and pitch of vias is important. For high speed interfaces, consider GND shielding vias. This via coupling is one factor for recommending data signals be routed on layers closest to processor.
  • via stubs affect signal integrity. via back-drilling can improve signal integrity, and is required in some instances.

For more information, see the High-Speed Interface Layout Guidelines application note. This provides additional general guidance for successful routing of high-speed signals.