SPRADP5 January   2026 AM62P , AM62P

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stack-Up
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References

4.2 Power Routing

The below 2D layout in Figure 4-1 and the 3D layout view in Figure 4-2 shows the VDDS_MMC0 power routing implemented on the SK-AM62P-LP (PROC164E2).

The 1.8V power rail for the AM62Px eMMC PHY supply VDDS_MMC0 and eMMC IO supply both originate from a common inductor from the PMIC switching regulator. In order to measure power of the SoC supplies independently of the eMMC, the VCC1V8_SYS supply crosses a shunt resistor and becomes SoC_DVDD1V8 before reaching the VDDS_MMC0 supply and other SoC supply pins.

The 2D layout indicates which layer is used for each shape and the 3D layout view clearly shows the vias used to transition layers. Solid GND planes exist on layers 2, 4, 6, and 11.

This layout was demonstrated through simulations to satisfy the power supply noise requirements to meet eMMC JEDEC specifications with margin. Further improvements such as solid GND on layer adjacent to VDDS_MMC0 supply, fewer layer transitions for the supply and/or additional vias between layer transitions should only help AC impedance performance and improve signal integrity margin. Board designers are encouraged to make the best PCB that is feasible.

SK-AM62P-LP (PROC164E2) eMMC Power Routing 2D Layout - VCC1V8_SYS (White) and SoC_DVDD1V8 (Purple) Figure 4-1 SK-AM62P-LP (PROC164E2) eMMC Power Routing 2D Layout - VCC1V8_SYS (White) and SoC_DVDD1V8 (Purple)
SK-AM62P-LP (PROC164E2) eMMC Power Routing 3D Layout - VCC1V8_SYS (White) and SoC_DVDD1V8 (Purple) Figure 4-2 SK-AM62P-LP (PROC164E2) eMMC Power Routing 3D Layout - VCC1V8_SYS (White) and SoC_DVDD1V8 (Purple)