SPRADT6 July   2026 AWR2944 , AWR2944P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to AWR294x and Safety Modules
  5. 2In-Depth Guide to AWR294x Safety Diagnostic Library
    1. 2.1  DPL Data Porting Layer
    2. 2.2  CCM Core Compare Module
    3. 2.3  DCC Dual Clock Comparator
    4. 2.4  ECC Error Correction Code
    5. 2.5  ECC Bus Safety
    6. 2.6  HWA Hardware Accelerator Safety
    7. 2.7  MCRC Cyclic Redundancy Check
    8. 2.8  Parity
    9. 2.9  PBIST Programmable Built-In Self-Test
    10. 2.10 Reset Management
    11. 2.11 ROM Checksum
    12. 2.12 RTI Real-Time Windowed Watchdog
    13. 2.13 STC Self-Test Controller
  6. 3Summary
  7. 4Glossary
  8. 5References

2.4 ECC Error Correction Code

The ECC module provides Single Error Correction (SEC) and Double Error Detection (DED) for on-chip memory through the ECC Aggregator and ECC Wrapper. Reference [1] states that the ECC Aggregator communicates with the ECC Wrapper of each memory via a serial interface, with the Wrapper responsible for actual ECC detection and correction. The AWR2944 chip contains 5 ECC Aggregators:

  • MSS_ECC_AGG_R5A (Cache/TCM/VIM of R5F Core A)
  • MSS_ECC_AGG_R5B (Cache/TCM/VIM of R5F Core B)
  • MSS_ECC_AGG_MSS (L2/MBOX/RETRAM/GPADC/TPTC)
  • DSS_ECC_AGG (L3/MBOX/TPTC)
  • HSM_ECC_AGGR (HWA)

Each Aggregator manages multiple RAM IDs, where each ID corresponds to an ECC-protected memory module.

Core features of the ECC Aggregator:

  • Reduces memory soft errors through ECC (SEC is correctable, DED is detectable but uncorrectable)
  • Supports parity checking on the serial FIFO interface
  • Control bits have redundancy protection, and a single-bit flip can trigger an interrupt
  • Supports Inject Only mode for diagnostic testing
  • Provides software-readable SEC/DED error status, containing row address and flipped bit position details

ECC testing covers 11 memory regions (r5_atcm0, r5_btcm, mss_l2, mss_tptc, mcan, dss_ecc_hwa, dss_l3_ecc, dss_mailbox, dss_tptc, dsp_edc, dss_l2_edc).

General test workflow:

  1. The R5F core executes SDL_EXCEPTION_init to register exception handlers.
  2. SDL_ECC_initMemory initializes ECC protection for the target RAM.
  3. Initializes the ESM and configures high- and low-priority interrupts.
  4. SDL_ECC_init initializes the ECC aggregator (specifying the RAM ID list).
  5. SDL_ECC_injectError injects single-/double-bit errors, waiting for the ESM interrupt.
  6. In the ESM callback, SDL_ECC_getESMErrorInfo and SDL_ECC_getErrorInfo are called to obtain detailed error information, followed by clearing the interrupt.
Table 2-7 ECC Module Function Descriptions
Key Function Functions
SDL_ECC_init Initializes the ECC aggregator, configuring the RAM subtype list
SDL_ECC_initMemory Initializes ECC protection for the specified RAM
SDL_ECC_injectError Injects SEC/DED errors into the specified memory
SDL_ECC_getESMErrorInfo Parses ECC error types from the ESM interrupt source
SDL_ECC_getErrorInfo Gets detailed ECC information (address, flipped bits, etc.)
SDL_ECC_clearNIntrPending Clears pending interrupts
SDL_ECC_ackIntr Acknowledges ECC interrupts
CAUTION: On the R5F, the exception handler (SDL_EXCEPTION_init) must be initialized first, otherwise DED may not be reported correctly.