SPRADT6 July   2026 AWR2944 , AWR2944P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to AWR294x and Safety Modules
  5. 2In-Depth Guide to AWR294x Safety Diagnostic Library
    1. 2.1  DPL Data Porting Layer
    2. 2.2  CCM Core Compare Module
    3. 2.3  DCC Dual Clock Comparator
    4. 2.4  ECC Error Correction Code
    5. 2.5  ECC Bus Safety
    6. 2.6  HWA Hardware Accelerator Safety
    7. 2.7  MCRC Cyclic Redundancy Check
    8. 2.8  Parity
    9. 2.9  PBIST Programmable Built-In Self-Test
    10. 2.10 Reset Management
    11. 2.11 ROM Checksum
    12. 2.12 RTI Real-Time Windowed Watchdog
    13. 2.13 STC Self-Test Controller
  6. 3Summary
  7. 4Glossary
  8. 5References

2.7 MCRC Cyclic Redundancy Check

MCRC (Memory Cyclic Redundancy Check) verifies memory data integrity through hardware-accelerated CRC calculation. This module uses a maximum 64-bit polynomial f(x) = x⁶⁴ + x⁴ + x³ + x + 1 to construct PSA (Parallel Signature Analysis) registers, performing calculations on 8/16/32/64-bit data widths.

MCRC supports two independent channels, which can perform CRC calculations on multiple memory regions in parallel and supports three modes:

Auto Mode: DMA automatically transfers data for CRC calculation without CPU involvement. When a mismatch occurs, an interrupt is generated, and the hardware provides a 16-bit sector ID to locate the faulty sector.

Semi-CPU Mode: DMA remains responsible for data transfer, but an interrupt is triggered after each sector compression is completed, prompting the CPU to read the signature register and manually compare it with the preset value.

Full-CPU Mode: The CPU is fully responsible—both transferring data to the signature register and reading the result for comparison. No interrupts, no DMA, and all counters are disabled.

Full-CPU Mode Testing (mcrc_full_cpu):

Table 2-10 MCRC Full-CPU Mode Workflow
Step Action Description
1 SDL_MCRC_init Initializes the MCRC channel
2 SDL_MCRC_channelReset Resets the CRC channel
3 SDL_MCRC_config Configures mode, pattern size, and sector count
4 Input raw data Writes known data patterns
5 SDL_MCRC_computeSignCPUmode Calculates the CRC signature
6 Compare signature Compares with the reference signature

Semi-CPU Mode Testing (mcrc_semi_cpu):

Table 2-11 MCRC Semi-CPU Mode Workflow
Step Action Description
1 SDL_MCRC_init Initializes the MCRC channel
2 SDL_MCRC_channelReset Resets the CRC channel
3 SDL_MCRC_config Configures the channel to Semi-CPU mode
4 EDMA operation Transfers data into PSA registers
5 Waiting for interrupt MCRC completes one sector compression
6 Read PSA Sector Signature Compares with the reference signature

Auto Mode Testing (mcrc_auto_cpu):

Table 2-12 MCRC Auto Mode Workflow
Step Action Description
1

SDL_MCRC_init

SDL_MCRC_channelReset

 Initializes and resets the MCRC channel
2 SDL_MCRC_config Sets SDL_MCRC_OPERATION_MODE_AUTO
3 EDMA transfer Transfers both data and pre-calculated signatures to the CRC Value Register
4 MCRC auto comparison Hardware completes signature comparison
5 Interrupt gets result CRC Fail interrupt or completion notification

Key Function Description:

Table 2-13 MCRC Module Function Descriptions
Key Function Functions
SDL_MCRC_init Initializes MCRC channels (watchdog/block preload values)
SDL_MCRC_channelReset Resets the CRC channel
SDL_MCRC_config Configures mode, pattern size, and sector count
SDL_MCRC_configCRCType Configures the CRC polynomial
SDL_MCRC_computeSignCPUmode Calculates CRC signature in Full-CPU mode
SDL_MCRC_getPSASigRegAddr Gets PSA signature register address
SDL_MCRC_getPSASectorSig Gets sector signature value
SDL_MCRC_getPSASig Reads PSA signature value
SDL_MCRC_enableIntr Enables MCRC interrupts