SPRADT6 July   2026 AWR2944 , AWR2944P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to AWR294x and Safety Modules
  5. 2In-Depth Guide to AWR294x Safety Diagnostic Library
    1. 2.1  DPL Data Porting Layer
    2. 2.2  CCM Core Compare Module
    3. 2.3  DCC Dual Clock Comparator
    4. 2.4  ECC Error Correction Code
    5. 2.5  ECC Bus Safety
    6. 2.6  HWA Hardware Accelerator Safety
    7. 2.7  MCRC Cyclic Redundancy Check
    8. 2.8  Parity
    9. 2.9  PBIST Programmable Built-In Self-Test
    10. 2.10 Reset Management
    11. 2.11 ROM Checksum
    12. 2.12 RTI Real-Time Windowed Watchdog
    13. 2.13 STC Self-Test Controller
  6. 3Summary
  7. 4Glossary
  8. 5References

2.5 ECC Bus Safety

ECC Bus Safety extends ECC protection from memory to bus interconnect modules. Reference [1] points out that the command/address buses on the system interconnect bus have parity checking and redundancy protection, while the data bus has SEC and DED protection. This module covers approximately 60 bus nodes in both MSS and DSS subsystems.

Testing is divided into three categories for each bus node: Single-Bit Error Correction (SEC), Double-Bit Error Detection (DED), and Redundancy Error Detection (RED). Coverage includes: TPTC read/write channels, DMA controllers, Mailbox, FIFO, CPSW, QSPI, GPADC, MCRC, and other modules.

Testing method: Triggers data read/write on the target bus node through EDMA transfer, injecting ECC errors and verifying the ESM response.

Table 2-8 ECC Bus Safety Module Function Descriptions
Key Function Functions
SDL_ECC_BUS_SAFETY_*_SEC_Test Single-bit error correction test for each node
SDL_ECC_BUS_SAFETY_*_DED_Test Double-bit error detection test for each node
SDL_ECC_BUS_SAFETY_*_RED_Test Redundancy error detection test for each node