SPRUJ07 august   2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x and F28P65x
    1. 1.1 F2837x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP and 100-Pin PZP Package
    2. 2.2 Use of Existing 176-Pin F2837x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins with Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 100-Pin PZP New PCB Design
    5. 2.5 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1 Lock-step Compare Module (LCM)
      2. 3.1.2 Expanded Analog Channels
      3. 3.1.3 Firmware Update (FWU)
      4. 3.1.4 Flexible GPIO and Digital Input Pins
      5. 3.1.5 ADC Hardware Redundancy Safety Checker
      6. 3.1.6 Flexible Memory Sharing between CPU Subsystems
      7. 3.1.7 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2837x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2837x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2837x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2837x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5EABI Support
    1. 5.1 NoINIT Struct Fix (Linker Command)
    2. 5.2 Pre-Compiled Libraries
  9.   References

2.4 100-Pin PZP New PCB Design

To enable early development on F28P65x using existing F2837x 100-Pin device, this supplemental section covers the dual routing technique as illustrated in Figure 2-5. The complete pin usage recommendation is outlined in Figure 2-2.

GUID-20220609-SS0I-1LCG-PK86-MVHFCGPVMRHP-low.svg Figure 2-5 Dual Routing Technique Illustrated

For the color legend, see Figure 2-2.

Table 2-7 Common 100-Pin PTP PCB Design for F2837x and F28P65x
Pin No Pin Name Transition Type Action
F2837x F28P65x F2837x to F28P65x F28P65x to F2837x
Minor Incompatibility - Signals in Common
17 VSSA/VREFLOA VSSA Common Analog Channel Use VSSA
20 ADCINA5 ADCINA5/AIO232 Use ADCINA5
21 ADCINA4 ADCINA4/AIO231 Use ADCINA4
22 ADCINA3 ADCINA3/AIO230 Use ADCINA3
23 ADCINA2 ADCINA2/AIO229 Use ADCINA2
24 ADCINA1 ADCINA1/AIO228 Use ADCINA1
25 ADCINA0 ADCINA0/AIO227 Use ADCINA0
26 ADCIN14 ADCIN14/AIO225 Use ADCIN14
27 ADCIN15 ADCIN15/AIO226 Use ADCIN15
28 ADCINB0 ADCINB0/AIO233 Use ADCINB0
29 ADCINB1 ADCINB1/AIO234 Use ADCINB1
30 ADCINB2 ADCINB2/AIO235 Use ADCINB2
31 ADCINB3 ADCINB3/AIO236 Use ADCINB3
46 TDI GPIO222/TDI Common JTAG Use TDI
47 TDO GPIO223/TDO Use TDO
Medium incompatibility - Dual routing(1)
7 GPIO16 VDDIO Populate 0 ohm resistor to VDDIO Populate 0 ohm resistor to GPIO
8 GPIO17 VDD Populate 0 ohm resistor to VDD
32 ADCINB4 VREFLOB Populate 0 ohm resistor to VREFLOB Populate 0 ohm resistor to ADC channel
33 ADCINB5 VSSA Populate 0 ohm resistor to VSSA
9 GPIO18 ADCINC0/GPIO199 Dual PCB Route, through 0-Ohm Resistor or DNP. Populate 0 ohm resistor to GPIO/AGPIO Populate 0 ohm resistor to GPIO
11 GPIO19 ADCINC6/GPIO203
12 GPIO20 ADCINC5/GPIO204
13 GPIO21 ADCINC4/GPIO205
14 GPIO99 ADCINC3/GPIO206
48 TRSTn GPIO30 Populate 0 ohm resistor to TRSTn
37 VREFHIB ADCINB7/GPIO208 Populate 0 ohm resistor to VREFHIB
39 VDD ADCINA10/GPIO213 Populate 0 ohm resistor to VDD
71 VDD GPIO46
84 VDD GPIO25
89 VDD GPIO0
15 VDDIO ADCINC2/AIO237 Populate 0 ohm resistor to VDDIO
10 VDDIO ADCINC1/GPIO200
40 VDDIO ADCINA11/GPIO214
72 VDDIO GPIO47
83 VDDIO GPIO80
90 VDDIO GPIO1
38 VDDA ADCINA6/GPIO209 Populate 0 ohm resistor to VDDA
33 VSSA ADCINB5 Populate 0 ohm resistor to VSSA
36 VSSA ADCINB6/GPIO207
42 FLT1 GPIO34 Populate 0 ohm resistor to FLT pads
43 FLT2 GPIO35
Major incompatibility (have to be isolated by 0 ohm resistor) - Dual routing(1)
16 VDD VREFLOC Dual PCB Route, through 0-Ohm Resistor or DNP. Populate 0 ohm resistor to VREFLO Populate 0 ohm resistor to VDD
34 VREFLOB VREFHIB Populate 0 ohm resistor to VREFHI Populate 0 ohm resistor to VREFLO
35 VSSA VDDA Populate 0 ohm resistor to VDDA Populate 0 ohm resistor to VSSA
1. Use Dual Routing example diagram in Figure 2-5
1. Use Dual Routing example diagram in Figure 2-5