Monitoring data movement and the memory architecture of a processor – in order to prevent various core blockages and delays when running multiple cores concurrently – can help maximize overall system performance.

TI vision AI processors have a high-bandwidth bus interconnect with a nonblocking infrastructure and large internal memory. Multiple dedicated programmable DMA engines automate data movement at very high speeds. This design enables high utilization of the hardware accelerators, with substantial double-data-rate (DDR) bandwidth savings. Reducing the number of DDR instances lowers the amount of power used by DDR access, thus lowering the overall system power consumption.