SPRZ530B april   2022  – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2063
      4.      i2064
      5.      i2065
      6.      i2079
      7.      i2091
      8.      i2097
      9.      i2103
      10.      i2120
      11.      i2134
      12.      i2137
      13.      i2146
      14.      i2157
      15.      i2159
      16.      i2160
      17.      i2161
      18.      i2163
      19.      i2166
      20.      i2177
      21.      i2189
      22.      i2190
      23.      i2196
      24.      i2197
      25.      i2205
      26.      i2215
      27.      i2216
      28.      i2219
      29.      i2232
      30.      i2234
      31.      i2235
      32.      i2237
      33.      i2242
      34.      i2243
      35.      i2244
      36.      i2245
      37.      i2249
      38.      i2253
      39.      i2271
      40.      i2272
      41.      i2278
      42.      i2279
      43.      i2283
      44.      i2307
      45.      i2308
      46.      i2310
      47.      i2311
      48.      i2312
      49.      i2313
      50.      i2316
      51.      i2320
      52.      i2326
      53.      i2329
      54.      i2351
      55.      i2362
      56.      i2366
      57.      i2371
      58.      i2372
      59.      i2378
      60.      i2381
      61.      i2383
  5.   Trademarks
  6.   Revision History

i2235

CBASS Null Error Interrupt Not Masked By Enable Register

Details

There is optional feature in CBASS that adds the null error reporting MMR and interrupt source. When the feature is present and the interrupt is enabled, these two output ports: "err_intr_intr" (level interrupt source) and "err_intr_pls_intr" (pulse interrupt source) will be asserted when an access to a null region occurs. The enable for the interrupt is in the ERR_INTR_ENABLE_SET register (address offset 0x58).

The issue is CBASS ignores this enable bit, and as a result any null access always produces the interrupt sources/events.

Workaround

There is no spurious event due to this bug because of the default disable status of processor events. At system level, processors don't receive any event unless it's enabled in the associated GIC/VIM interrupt controller.

When the interrupt is enabled, and an interrupt does occur, write to the following registers at cbass level to clear it:

write 0x1 to the err_intr_enabled_stat register, then write 0x1 to the err_eoi register.