SPRZ530B april   2022  – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2063
      4.      i2064
      5.      i2065
      6.      i2079
      7.      i2091
      8.      i2097
      9.      i2103
      10.      i2120
      11.      i2134
      12.      i2137
      13.      i2146
      14.      i2157
      15.      i2159
      16.      i2160
      17.      i2161
      18.      i2163
      19.      i2166
      20.      i2177
      21.      i2189
      22.      i2190
      23.      i2196
      24.      i2197
      25.      i2205
      26.      i2215
      27.      i2216
      28.      i2219
      29.      i2232
      30.      i2234
      31.      i2235
      32.      i2237
      33.      i2242
      34.      i2243
      35.      i2244
      36.      i2245
      37.      i2249
      38.      i2253
      39.      i2271
      40.      i2272
      41.      i2278
      42.      i2279
      43.      i2283
      44.      i2307
      45.      i2308
      46.      i2310
      47.      i2311
      48.      i2312
      49.      i2313
      50.      i2316
      51.      i2320
      52.      i2326
      53.      i2329
      54.      i2351
      55.      i2362
      56.      i2366
      57.      i2371
      58.      i2372
      59.      i2378
      60.      i2381
      61.      i2383
  5.   Trademarks
  6.   Revision History

Revision History

Changes from September 8, 2022 to June 10, 2023 (from Revision A (September 2022) to Revision B (June 2023))

  • Added Advisory i2243; PCIe: Timing requirement for disabling output refclk during L1.2 substate is not metGo
  • Added Advisory i2243; PCIe: Timing requirement for disabling output refclk during L1.2 substate is not metGo
  • Added Advisory i2249; OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperableGo
  • Added Advisory i2253; PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failureGo
  • Added Advisory i2283; Restrictions on how CP Tracer Debug Probes can be usedGo
  • Added Advisory i2312; MMCSD: HS200 and SDR104 Command Timeout Window Too SmallGo
  • Added Advisory i2316; DDR: MCU_OSPI0_* pins are limited to 1.8V operation when DDR1 is usedGo
  • Added Advisory i2326; PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limitsGo
  • Added Usage Note i2351; OSPI: Controller does not support Continuous Read mode with NAND FlashGo
  • Added Advisory i2362; 10-100M SGMII: Marvell PHY does not ignore the preamble byte resulting in link failureGo
  • Added Advisory i2366; Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operationGo
  • Added Advisory i2371; Boot: ROM code may hang in UART boot mode during data transferGo
  • Added Usage Note i2372; Boot: ROM doesn't support select multi-plane addressing schemes in Serial NAND bootGo
  • Added Advisory i2378; MSMC: Cache/snoop filter way selection MMRs have incorrect reset valuesGo
  • Added Advisory i2381; MSMC: FFI reset allows target port to have backdoor access to the L3 data cache as mapped SRAMGo
  • Added Advisory i2383; OSPI: 2-byte address is not supported in PHY DDR modeGo