Revision
History
Changes from September 8, 2022 to June 10, 2023 (from Revision A (September 2022) to Revision B (June 2023))
- Added Advisory i2243; PCIe: Timing requirement for disabling output refclk
during L1.2 substate is not metGo
- Added Advisory i2243; PCIe: Timing requirement for disabling output refclk
during L1.2 substate is not metGo
- Added Advisory i2249; OSPI: Internal PHY Loopback and Internal Pad Loopback
clocking modes with DDR timing inoperableGo
- Added Advisory i2253; PRG: CTRL_MMR STAT registers are unreliable indicators
of POK threshold failureGo
- Added Advisory i2283; Restrictions on how CP Tracer Debug Probes can be
usedGo
- Added Advisory i2312; MMCSD: HS200 and SDR104 Command Timeout Window
Too SmallGo
- Added Advisory i2316; DDR: MCU_OSPI0_* pins are limited to 1.8V operation
when DDR1 is usedGo
- Added Advisory i2326; PCIe: MAIN_PLLx operating in fractional mode,
which is required for enabling SSC, is not compliant with PCIe Refclk jitter
limitsGo
- Added Usage Note i2351; OSPI: Controller does not support Continuous
Read mode with NAND FlashGo
- Added Advisory i2362; 10-100M SGMII: Marvell PHY does not ignore the
preamble byte resulting in link failureGo
- Added Advisory i2366; Boot: ROM does not comprehend specific JEDEC
SFDP features for 8D-8D-8D operationGo
- Added Advisory i2371; Boot: ROM code may hang in UART boot mode
during data transferGo
- Added Usage Note i2372; Boot: ROM doesn't support select multi-plane
addressing schemes in Serial NAND bootGo
- Added Advisory i2378; MSMC: Cache/snoop filter way selection MMRs have
incorrect reset valuesGo
- Added Advisory i2381; MSMC: FFI reset allows target port to have backdoor
access to the L3 data cache as mapped SRAMGo
- Added Advisory i2383; OSPI: 2-byte address is not supported in PHY DDR
modeGo