STDA039 July 2026 F28377D-SEP , INA901-SP , SN54SLC8T245-SEP , TPS7A4501-SP , TPS7H1121-SEP , TPS7H1121-SP , TPS7H5020-SEP , TPS7H5020-SP , TPS7H6101-SEP
The goal of SEE testing is to find out how a device reacts when the device is struck by a single particle—such as a heavy ion or proton in space, a neutron on Earth, or an alpha particle from packaging materials.
SEE tests are normally carried out at an accelerator facility capable of generating high energy heavy ions or protons. The device under test (DUT) is powered up and operated under the normal bias and functional conditions for the device. During the test, key parameters such as supply current and output status are monitored continuously. While the DUT is exposed to the ion or proton beam, any transient changes in current or output are recorded.
For space applications, performance under heavy ion radiation is a major concern. If a device is sensitive to low energy heavy ions, the device is likely also sensitive to high energy protons. Consequently, space qualification programs usually employ heavy ion or proton beams. For research purposes, other localized charge injection sources—such as pulsed lasers—can also be used.
In a heavy ion test, the DUT is placed directly in the ion beam and the DUT operation is observed in real time. The beam is produced by a particle accelerator (for example, a cyclotron or Van de Graaff generator). In orbit, heavy ions can have enough energy to traverse a packaged IC and any shielding present. Most test facilities, however, can only deliver ions with enough energy to penetrate 40µm–400µm of silicon, which is insufficient to go through a fully sealed package. Therefore, the package must be opened to expose the die while the device remains functional.
Typical methods for exposing the die include:
| Method | Description | Typical applicability |
|---|---|---|
| Jet etching | Selective chemical etching | Removes package material locally to uncover the die | Widely used for small‑die, low‑pin-count parts |
| Pre‑thinning | Thins the package to a few microns before testing | Appropriate for thin‑film or MEMS devices |
| Hybrid approaches | Combination of etching and thinning for 3D structures | Required for stacked or heterogeneous ICs |
| Flip‑chip preparation | Removes the substrate and bonds the die directly to a test board | Used for high‑performance or high‑pin‑count devices |
Each technique requires specific expertise; in some cases a particular method is not applicable, and occasionally the device architecture (for example, with 3D stacking) simply does not allow die exposure while maintaining functionality. TESAT reports that roughly 10% of the candidates examined so far had to be discarded for this reason. An example of an opened device is shown below in Figure 4-1.
Figure 4-1 Exposing the Die is Far from
Being a Trivial Task