During actual SEE testing at 60MeV, the typical attrition pattern is:

• ≅25 % of the remaining candidates fail outright.
• ≅50 % pass but only with constraints (for example, limited voltage, temperature range, drifts, and so forth).
• ≅25 % pass without any constraints, leaving usually three devices from the originally assumed five candidates for further evaluation.

Figure 4-2 Power FETs (MOSFETs) or Power Devices in General Have a Significantly Lower Success Probability

Further, complex ICs such as MCUs or ADCs—with many configuration options—require sophisticated test software. In practice a tradeoff must be made between the effort invested in developing a comprehensive test program and the time and residual risk incurred by incomplete test coverage. Typically, the test program ends up being rather use-case specific, which needs to be kept in mind if the results are considered for future designs and use cases as well.