SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The ADC core uses an internal 24 MHz clock for sampling and conversion. This internal clock source is required to enable the ADC core clock to use the ADC. For a description, see AUX_SYSIF:ADCCLKCTL in Section 20.8.9.
Once the ADC clock is requested, the clock source follows from Table 20-32.
RCOSC_HF | XOSC_HF | ADC Clock Source |
---|---|---|
Off | Off | RCOSC_HF |
Off | On | XOSC_HF |
On | Off | RCOSC_HF |
On | On | XOSC_HF |
For accurate, low-jitter sampling in asynchronous mode, software must ensure that SCLK_HF is sourced from the 24 MHz crystal.
When the ADC clock is enabled, the system cannot go into standby or shutdown mode because the power controller requests a high-frequency clock source.
Finally, the user must set ADI_4_AUX:ADC0.EN to enable the analog ADC core and enable reaction to ADC triggers.