TIDUDI9A January   2018  – May 2025 ISOM8610

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 ISO121x
      2. 2.2.2 SN74LV165A
      3. 2.2.3 SN74LVC1GU04
      4. 2.2.4 TVS3300
      5. 2.2.5 ISOM8600
    3. 2.3 System Design Theory
      1. 2.3.1 Digital Input Stage
      2. 2.3.2 Broken Wire Detection
        1. 2.3.2.1 Case 1: Wire Intact and Input State '1'
        2. 2.3.2.2 Case 2: Wire Intact and Input State '0'
        3. 2.3.2.3 Case 3: Broken Wire
      3. 2.3.3 Readout of Digital Outputs
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Group-Channel Configuration
        2. 3.2.2.2 Single-Channel Configuration
      3. 3.2.3 Conclusion
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Software Files
  12. 6Related Documentation
    1. 6.1 Trademarks
  13. 7About the Author
    1. 7.1 Acknowledgments
  14. 8Revision History

2.3.3 Readout of Digital Outputs

To readout the 16 digital output signals, there are two options:

  1. Parallel readout of output signals at connectors J5 (channels 1–8) and J8 (channels 9–16)
  2. Serial readout of output signals from parallel-in serial-out registers U1 and U2
TIDA-01509 Schematic of Parallel and Serial Readout Options for Output Signals Figure 2-11 Schematic of Parallel and Serial Readout Options for Output Signals

For serial readout, all eight output signals per group are connected to the parallel-in serial-out register SN74LV165A. The output QH of register U1 is connected to input pin SER of register U2. To readout the register, the SPI of the LaunchPad is used. For this, the LaunchPad SPI is connected to the SN74LV165A registers as follows:

Note:

The SPI_nCS signal of the LaunchPad is inverted using a logic gate SN74LVC1GU04 with function Y = A.

→ SPI_nCS logic '0' / low = logic '1' / high at SH/ LD pin of SN74LV165A

Table 2-2 Electrical Connections Between SPI and U1, U2
LAUNCHPAD U1 (CHANNELS 1–8) U2 (CHANNELS 9–16)
SPI_MOSI Not used Not used
SPI_MISO Not connected QH
SPI_nCS SH/ LD SH/ LD
SPI_CLK CLK CLK
QH SER

The readout of the 16 output states works as follows:

  1. SPI_nCS is high → both SN74LV165A continuously load input states
  2. SPI_nCS pulled low → both SN74LV165A store current status of their respective eight inputs
  3. SPI_CLK is clocked 16 times → output QH of register U2 first gives out outputs states of inputs H–A (channel 9–16) of U2, second gives out output states H–A (channel 1–8) of U1.