The DAC11001B is an enhanced version of the DAC11001A. These enhancements include lower integral nonlinearity (INL) and an improved track-and-hold circuit (TnH).

INL, also called relative accuracy, measures the difference between the actual DAC output and the expected theoretical output for each code. This parameter is commonly noted in least significant bits, or LSBs. Mathematically, INL is the sum of each individual code-to-code error of previous codes. The DAC11001A has a maximum 4LSB error, this means an individual code has the potential of being up to four LSBs away from the best possible output, not including offset and gain error. The DAC11001B has maximum 1LSB error, providing a significantly more accurate output. Figure 2-12 and Figure 2-13 show the INL comparison from the two datasheets.

The DAC11001A and DAC1001B both implement track-and-hold subcircuits to reduce the impact of code-to-code glitch. As described in the Output Glitch section, the TnH circuit separates the output from the R-2R ladder during a DAC update with a switch. This switch is a complementary PMOS or NMOS structure. These MOSFETs can turn into parasitic diodes when the voltage across the switch is higher than some threshold. In the DAC11001A, Figure 2-14 shows that the TnH causes the output to slew when the differential voltage is greater than around 1V. This limitation is improved on the DAC11001B, as shown in Figure 2-15.

This TnH issue directly impacts THD+N through output distortion. Three parameters effect the DAC11001A TnH circuit: sample rate, output amplitude, and tone frequency. A low sample rate increases the time between output updates, potentially resulting in larger voltage steps between DAC updates. A larger DAC output range directly increases the voltage change amplitude. With a constant sample rate, increasing the tone frequency can cause the output to require larger voltage changes. Any of these affected parameters can be addressed by giving sufficient headroom in the other parameters. For example, a high output range is less likely to cause an issue if the sample rate is sufficiently high.

Figure 2-16 shows how these different parameters affect the THD+N of the DAC11001A and DAC11001B across the frequency spectrum. The figure compares the 0dB and –30dB amplitudes of the two DACs. The 0dB output range of the reference design is ±3V. All four data sets are measured with a constant sample rate of 192kSPS. At 0dB, DAC11001A starts degrading in THD+N at 1kHz. As the frequency increases, the voltage change amplitude with each update increases, and this causes the track-and-hold circuit to produce more distortion. The DAC11001B does not start degrading until 5kHz due to the improved TnH circuit. In the –30dB DACs, the THD+N measurements do not degrade until 10kHz. The lower amplitude reduces the maximum amplitude of the voltage update changes, and in turn prevents the additional TnH distortion. While the TnH circuit does not produce distortion, the overall THD+N measurements are worse with the –30dB amplitude because the DAC output amplitude is closer to the noise floor.