TIDUEV2 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Differences Between Audio DACs and Precision DACs
      2. 2.2.2 Right-Justified I2S to Daisy-Chained SPI Conversion
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC11001
      2. 2.3.2 OPA1656
      3. 2.3.3 OPA1622
      4. 2.3.4 OPA2828
    4. 2.4 System Design Theory
      1. 2.4.1 Output Glitch
      2. 2.4.2 Sample Rate Dependence in Precision DACs
      3. 2.4.3 System Noise
      4. 2.4.4 DAC11001A vs DAC11001B
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Required External Power Supplies
      2. 3.1.2 Jumper Definitions
      3. 3.1.3 Selecting I2S Source
        1. 3.1.3.1 USB I2S Source
        2. 3.1.3.2 SPDIF I2S Source
        3. 3.1.3.3 External PSIA I2S Source
    2. 3.2 Software Requirements
      1. 3.2.1 Installing the XMOS USB 2.0 Driver
      2. 3.2.2 Setting USB Sample Rate
    3. 3.3 Testing and Results
      1. 3.3.1 Measuring Total Harmonic Distortion and Noise
      2. 3.3.2 THD and THD+N Results
      3. 3.3.3 Measuring Dynamic Range
      4. 3.3.4 Dynamic Range Results
      5. 3.3.5 Measuring Signal-to-Noise Ratio
      6. 3.3.6 SNR Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Related Documentation
    1. 5.1 Support Resources
    2. 5.2 Trademarks
  12. 6About the Author

Output Glitch

Glitch is a major contributing factor in THD performance. Minimizing glitch is therefore required for high-fidelity audio performance. The main contributor of glitch in R-2R DACs comes from the R-2R switch network.

Typically, R-2R DAC architectures have each bit of resolution comprised of two resistors (R and 2R) and a switch that connects the resistor pair to the DAC positive reference or negative reference voltage. Figure 2-4 shows a simplified example. This architecture acts as a binary-weighted voltage divider. When the relative bit is high, the switch connects the R-2R pair to the positive reference. When the bit is low, the pair is connected to the negative reference.

TIDA-060031 R-2R Switch Architecture Figure 2-4 R-2R Switch Architecture

DAC glitch is defined as the energy associated with the overshoot or undershoot created by a code transition of a DAC. This glitch can occur even when just transitioning one code. Glitch energy is the result of charge injection from the R-2R switches. In R-2R DACs, code update glitches are large due to each switch representing a bit. The code-to-code glitch is dependent on the number of switches in the resistor ladder changing during a code transition. More individual bits changing results in higher glitch. The worst case code-to-code glitch is found at the mid-scale code transition at code 0x7FFFF and 0x80000 in a 20-bit device. In addition, the R-2R ladder commonly requires the use of larger switches which have larger capacitance. The higher capacitance increases the charge injection of each of the switches. Most R-2R DACs feature a two-lobe glitch output, where the output has a small overshoot into a large undershoot when the DAC output increases. This over- and undershoot is characteristic of the R-2R switches opening and then closing. Figure 2-6 shows an example of two-lobe glitch. The code-dependent glitch energy is detectable in the output spectrum as increases in higher-order harmonics or as additional spurs at non-harmonic frequencies.

TIDA-060031 R-2R Switches Mid-Scale Code
            TransitionFigure 2-5 R-2R Switches Mid-Scale Code Transition
TIDA-060031 R-2R Output GlitchFigure 2-6 R-2R Output Glitch

The DAC11001 devices feature a complex and high-performing track-and-hold (TnH) circuit to reduce the code-to-code glitch impacts of the 20-bit, R-2R resistor ladder used in the device. Figure 2-7 shows this circuit. The circuit features a switch and a sample capacitor on the output of the R-2R ladder. When the DAC code updates, the track-and-hold switch opens before the R-2R ladder changes. The sample capacitor holds the voltage stable at the initial voltage, shown as VPOST-TnH. After the R-2R ladder has finished updating, the track-and-hold switch closes, updating the output voltage. The track-and-hold circuit significantly reduces the glitch when the DAC changes at the expense of the DAC update rate. Figure 2-8 shows a comparison of the output glitch with the track-and-hold enabled and disabled.

TIDA-060031 DAC11001 Track-and-Hold Diagram Figure 2-7 DAC11001 Track-and-Hold Diagram
TIDA-060031 DAC11001 Track-and-Hold Enabled vs
          Disabled Figure 2-8 DAC11001 Track-and-Hold Enabled vs Disabled

The effectiveness of the TnH circuit is tested by measuring THD+N with the circuit on and off using a 1kHz tone at a sample rate of 192kSPS. With the TnH circuit on, the THD+N measurement is –107dB. With the circuit off, the THD+N measurement is –73dB. This is a difference of 34dB, or roughly 50 times worse performance.

Additionally, whenever the R-2R switches change position, the reference input impedance changes. Figure 2-9 shows the code-to-code change effect on the reference. This sudden impedance change causes a small glitch on the reference in the form of a voltage droop. While the track-and-hold circuit helps mitigate this glitch, it is important that the reference settles before the track-and-hold switch opens. Fast-settling reference buffers are required to minimize the glitch from the reference.

TIDA-060031 Reference Current vs DAC Code Figure 2-9 Reference Current vs DAC Code