TIDUEV2 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Differences Between Audio DACs and Precision DACs
      2. 2.2.2 Right-Justified I2S to Daisy-Chained SPI Conversion
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC11001
      2. 2.3.2 OPA1656
      3. 2.3.3 OPA1622
      4. 2.3.4 OPA2828
    4. 2.4 System Design Theory
      1. 2.4.1 Output Glitch
      2. 2.4.2 Sample Rate Dependence in Precision DACs
      3. 2.4.3 System Noise
      4. 2.4.4 DAC11001A vs DAC11001B
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Required External Power Supplies
      2. 3.1.2 Jumper Definitions
      3. 3.1.3 Selecting I2S Source
        1. 3.1.3.1 USB I2S Source
        2. 3.1.3.2 SPDIF I2S Source
        3. 3.1.3.3 External PSIA I2S Source
    2. 3.2 Software Requirements
      1. 3.2.1 Installing the XMOS USB 2.0 Driver
      2. 3.2.2 Setting USB Sample Rate
    3. 3.3 Testing and Results
      1. 3.3.1 Measuring Total Harmonic Distortion and Noise
      2. 3.3.2 THD and THD+N Results
      3. 3.3.3 Measuring Dynamic Range
      4. 3.3.4 Dynamic Range Results
      5. 3.3.5 Measuring Signal-to-Noise Ratio
      6. 3.3.6 SNR Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Related Documentation
    1. 5.1 Support Resources
    2. 5.2 Trademarks
  12. 6About the Author

2.4.2 Sample Rate Dependence in Precision DACs

A higher sample rate decreases DAC output distortion by reducing quantization noise. Precision DACs, unlike high-speed DACs and audio DACs, have low sample rates of typically less than 1MSPS. Precision DACs have a threshold where sample rate is limited by the output settling time. The output buffer must be able to settle within each DAC code update to prevent output signal distortion.

Devices that feature a track-and-hold circuit have additional barriers to high sample rates. The track-and-hold circuit has a set amount of time for the switch to remain open after each DAC update. The output distorts if the sample rate exceeds the track-and-hold sample period.

Delta-sigma designs feature other forms of error averaging, so these DACs do not have this track-and-hold limitation.