TIDUEV2 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Differences Between Audio DACs and Precision DACs
      2. 2.2.2 Right-Justified I2S to Daisy-Chained SPI Conversion
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC11001
      2. 2.3.2 OPA1656
      3. 2.3.3 OPA1622
      4. 2.3.4 OPA2828
    4. 2.4 System Design Theory
      1. 2.4.1 Output Glitch
      2. 2.4.2 Sample Rate Dependence in Precision DACs
      3. 2.4.3 System Noise
      4. 2.4.4 DAC11001A vs DAC11001B
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Required External Power Supplies
      2. 3.1.2 Jumper Definitions
      3. 3.1.3 Selecting I2S Source
        1. 3.1.3.1 USB I2S Source
        2. 3.1.3.2 SPDIF I2S Source
        3. 3.1.3.3 External PSIA I2S Source
    2. 3.2 Software Requirements
      1. 3.2.1 Installing the XMOS USB 2.0 Driver
      2. 3.2.2 Setting USB Sample Rate
    3. 3.3 Testing and Results
      1. 3.3.1 Measuring Total Harmonic Distortion and Noise
      2. 3.3.2 THD and THD+N Results
      3. 3.3.3 Measuring Dynamic Range
      4. 3.3.4 Dynamic Range Results
      5. 3.3.5 Measuring Signal-to-Noise Ratio
      6. 3.3.6 SNR Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Related Documentation
    1. 5.1 Support Resources
    2. 5.2 Trademarks
  12. 6About the Author

2.2.2 Right-Justified I2S to Daisy-Chained SPI Conversion

Audio devices primarily use the Inter-Integrated Circuit Sound (I2S) protocol for communication. I2S features a bit clock (BCLK), a left-right clock (LRCLK), and a data line. For ease of use, the TIDA-060031 features onboard digital logic to convert a 24-bit, right-justified I2S input into a two-frame daisy-chained SPI output. The DACs are set up in a daisy-chain configuration. This output is latched by the two DAC11001 devices. Figure 2-2 shows the I2S input overlaid with the desired SPI output.

TIDA-060031 I2S to Daisy-Chained SPI Figure 2-2 I2S to Daisy-Chained SPI

There are some key design challenges to overcome when creating the I2S-to-SPI digital logic.

  • The SPI clock is inverted compared to the I2S clock.
  • The 8 most-significant bits in the I2S frame are don't-cares while the DAC11001 requires this to be the DAC address, 0x01. This is accomplished with the SN74LV165APW, an 8-bit parallel load shift register.
  • The four least significant bits (LSBs) for the DAC11001 are don't-cares. This is not a major issue as 24-bit data is common in I2S, so no shifting is necessary.
  • The LRCK is 50% duty-cycle signal, while the DAC11001 requires an active-low chip select line. The LRCLK is delayed and inverted, and then ANDed with the original LRCLK to produce the CS-high pulse required by the DAC11001s.
  • An LDAC signal must be generated for the DACs to latch the data at same time.
  • The data value in I2S is a signed 24-bit integer, while the DAC11001A requires an unsigned integer. This means the most-significant bit of the data value must be inverted.

The TIDA-060031 implemented I2S-to-SPI conversion using the logic shown in Figure 2-3.

TIDA-060031 Digital Logic for I2S-to-SPI Conversion Figure 2-3 Digital Logic for I2S-to-SPI Conversion