TIDUFF7A October   2025  – March 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AM2612
      2. 2.3.2 DRV7167A
      3. 2.3.3 AMC0106M05
      4. 2.3.4 DP83826A
  9. 3System Design Theory
    1. 3.1 AM2612 Motor Control and Communication Interface
    2. 3.2 DC Link and Ground Configuration
    3. 3.3 Three-Phase Inverter With DRV7167A Half-Bridge GaN Motor Driver Power Stage
    4. 3.4 Inline Shunt Precision Phase-Current Sensing With AMC0106M05 Functionally Isolated, Delta-Sigma Modulator
    5. 3.5 System Power Management
    6. 3.6 Functional Safety Concept
    7. 3.7 Ethernet Physical Layer
    8. 3.8 Position Feedback Interface
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 TIDA-010979 PCB Overview
      2. 4.1.2 TIDA-010979 Hardware Setting
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Power Management and System Power Up and Power Down
      2. 4.4.2 Half-Bridge GaN Motor Driver Power Stage Switch Node
      3. 4.4.3 Power Stage Thermal Measurements
      4. 4.4.4 Phase-Current Sensing and Position Feedback
      5. 4.4.5 EtherCAT® Communication
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layout Prints
      4. 5.1.4 Altium Project
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

3.2 DC Link and Ground Configuration

The nominal 48V DC input voltage is buffered with seventeen 10μF ceramic capacitors to get a total of 170μF DC-bus capacitance. The PCB employs two separated ground planes: the power ground (PGND) and the logic or analog ground (GND). Both ground planes are connected in a star configuration through net ties to minimize the crosstalk of high switching frequency currents in the power ground plane into the logic plane. Figure 3-3 shows the DC-link decoupling and ground configuration schematic.

TIDA-010979 DC-Link Decoupling and Ground (GND) Configuration Figure 3-3 DC-Link Decoupling and Ground (GND) Configuration