This design leverages three DRV7167A 100V pulsed, 70A half-bridge power stage devices, with integrated gate-driver, enhancement-mode GaN FETs and short-circuit protection. The PCB space is further reduced due to high integration and the fact that only a few additional passive components are required. Figure 3-4 shows the schematic of one half-bridge.

Figure 3-4 Half-Bridge Power Stage Schematic for Phase A

The 48V DC-link voltage is connected to the DRV7167A VM pin and referenced to the power ground (PGND) pin. Local ceramic bypass capacitors C195, C196, C197, and C198 (1nF) are placed in parallel close between the VM and PGND pins to minimize loop inductance.

The DRV7167A integrated gate driver is supplied with 5V. A 10μF and 0.1μF ceramic bypass capacitor (C193, C194) are placed close to the GVDD pin and GND pin, as suggested in the datasheet.

Sequencing is not required for the 5V at GVDD and the 48V at VM, neither during the power up nor power down of the DC voltage input.

A 4.7μF ceramic bootstrap capacitor (C205) is placed close to the BOOT and HS (high-side GaN-FET source connection) pins. R165, R169, R168, and R173 are placed to configure the slew rate of the switch node rising and falling edge. The slew rate control resistors for the tests are 8.06kΩ which equals 2.6Ω gate resistors.

The complementary PWM signals for the high-side and low-side switch from the PWM buffer are low-pass filtered with R166, C207 and R170, and C208 to reject high-frequency impulse noise and avoid false switching with a cutoff frequency of around 160MHz and a propagation of around 1ns. The OUT pin is connected to the motor phase A terminal through a series inline shunt for phase-current sensing, and respectively for the other DRV7167A half-bridges to the phase B and the phase C terminal.

The DRV7167A implements three kinds of protection:

• Short-circuit protection – implements drain-to-source voltage monitoring based short-circuit protection on both FETs which operate on a cycle-by-cycle basis.
• Undervoltage detection – implements UVLO on both the GVDD and BOOT supplies. When the GVDD voltage is below the threshold voltage of 3.8V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. When the BOOT to HS bootstrap voltage is below the UVLO threshold of 3.2V, only the high-side GaN FET gate is pulled low.
• Overtemperature detection – monitors the die temperature of the integrated gate-driver and indicates a fault when the threshold is exceeded. The device does not take any other action, leaving any such protection action to the external PWM controller.

These faults are indicated on the DRVOFF/FLT pin which is the open-drain output. Once asserted, the active low fault signal remains asserted as long any of the three faults exist.