Positive-edge and negative-edge triggered JK flip-flops
Resolve common synchronous logic and memory issues such as synchronizing digital signals, converting momentary switches to toggle switches, or holding signals during reset with our portfolio of more than 40 JK flip-flops. Included are CMOS and TTL-compatible CMOS options.
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Benefits of our JK flip-flops
Rated for space
Our strong portfolio of products support extended temperature range as well as space rating.
Diverse package offering
Leaded and leadless ceramic or plastic packages available with pin counts ranging from 14 to 20 pins
Wide range of JK flip-flop functions
Fulfill your design needs with negative-edge or positive-edge triggering
Common applications of JK flip-flops
Control digital signals
Digital signals sometimes need to be enabled or disabled during system operation. This video explores all the options for what to do with the output when a line is disabled, and identifies logic devices that can perform each function.
A generic CMOS input structure is discussed along with it's typical characteristics and behavior. Use cases for Logic gates are discussed as well.
This section discusses a typical CMOS output structure and its characteristics. Based on the understanding of the CMOS output structure, use cases are discussed.
LOGIC Pocket Data Book (Rev. B)
This Logic reference manual equips the engineer with fundamental information to improve Logic implementation in designs.