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Product details

Parameters

Function Parity Bits (#) 9 Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type CMOS open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Inputs Are TTL-Voltage Compatible
  • Generates Either Odd or Even Parity for Nine Data Lines
  • Cascadable for n-Bits Parity
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)

 

EPIC is a trademark of Texas Instruments Incorporated.

open-in-new Find other Counter, arithmetic & parity function ICs

Description

The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The control input is implemented specifically to accommodate cascading. When the is low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.

The 74ACT11286 is characterized for operation from -40°C to 85°C.

 

open-in-new Find other Counter, arithmetic & parity function ICs
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 9-Bit Parity Generator/Checker With Bus Driver Parity I/O Ports datasheet (Rev. B) Apr. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options

Ordering & quality

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