Packaging information
| Package | Pins SOIC (DW) | 24 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 25 | TUBE |
Features for the 74ACT11373
- Eight Latches in a Single Package
- 3-State Bus Driving True Outputs
- Full Parallel Access for Loading
- Buffered Input and Output-Enable Pins
- Inputs Are TTL-Voltage Compatible
- Flow-Through Architecture Optimizes PCB Layout
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)
EPIC is a trademark of Texas Instruments Incorporated.
Description for the 74ACT11373
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
A buffered output-enable 
input can be used to place the eight outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impendance third state and increased
drive provide the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components.
does not affect
the internal operations of the latches. Old data can be retained or
new data can be entered while the outputs are off.
The 74ACT11373 is characterized for operation from -40°C to 85°C.