Product details

Bits (#) 4 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18
Bits (#) 4 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18
PDIP (N) 14 181 mm² 19.3 x 9.4
  • One standard "B" output will drive eight terminator circuits.
  • Will terminate a CMOS data bus with up to 40 B-series inputs inputs or 3-state outputs connected at VDD of 5 V.
  • Input terminal protected by standard "B" series ESD protection network.
  • Preserves final logic state.
  • Output after switching is closer to VDD or VSS rail than with a resistor.
  • Requires only one solder connection.
  • Open circuited terminator not used will not affect performance.
  • Can be connected to any CMOS I/O line.
  • Draws current only when logic state is changing.
  • Can be preset.
  • Applications
    • Error state identification.
    • Replaces pull-up or pull-down resistors
    • Avoids floating inputs in modular systems
    • Sharpens transistors (hysteresis)
    • Anti-bounce circuit

NOT RECOMMENDED FOR NEW DESIGNS

  • One standard "B" output will drive eight terminator circuits.
  • Will terminate a CMOS data bus with up to 40 B-series inputs inputs or 3-state outputs connected at VDD of 5 V.
  • Input terminal protected by standard "B" series ESD protection network.
  • Preserves final logic state.
  • Output after switching is closer to VDD or VSS rail than with a resistor.
  • Requires only one solder connection.
  • Open circuited terminator not used will not affect performance.
  • Can be connected to any CMOS I/O line.
  • Draws current only when logic state is changing.
  • Can be preset.
  • Applications
    • Error state identification.
    • Replaces pull-up or pull-down resistors
    • Avoids floating inputs in modular systems
    • Sharpens transistors (hysteresis)
    • Anti-bounce circuit

NOT RECOMMENDED FOR NEW DESIGNS

CD40117B is a dual 4-bit terminator that can be programmed by means of STROBE and DATA control bits to function as pull-up or pull-down resistors. The CD40117B can also be programmed to function as latches to terminate any open or unused CMOS logic when used with 3-state logic or during a power-down condition. Considerable savings in power and board space can be realized when this device is used to replace pull-up or pull-down resistors. When the STROBE is in the logic "1" state, the terminator functions as a pull-up resistor if the DATA input is a logic "1" or as a pull down resistor if the DATA input is a logic "0".

When the STROBE is in the logic "0" state, the terminator performs the latch functions, i.e., it follows the changing states of the bus. If the bus goes into the high-Z state or into a power-down condition, the latched terminator retains the data ("1" or "0") that the bus carried before it switched to the high-Z or power-down state. If and when the bus changes from the high-Z state to the state opposite to that which the latch is storing, the bus will override the latch and the terminator will reflect the state on the bus. The small geometries chosen for the inverters in the latch allow this override mode. When checking the data bus whose last state is being preserved by the terminator, a resistor should be used in series with the probe whose input capacitance could trip the small latches. The resistance should be in excess of the output impedance of the latch, i.e., R should be > 30 K at VDD = 10 V.

The STROBE and DATA inputs in each section can be paralleled allowing this device to be used as an 8-bit bus terminator.

The CD40117B types are supplied in 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40117B is a dual 4-bit terminator that can be programmed by means of STROBE and DATA control bits to function as pull-up or pull-down resistors. The CD40117B can also be programmed to function as latches to terminate any open or unused CMOS logic when used with 3-state logic or during a power-down condition. Considerable savings in power and board space can be realized when this device is used to replace pull-up or pull-down resistors. When the STROBE is in the logic "1" state, the terminator functions as a pull-up resistor if the DATA input is a logic "1" or as a pull down resistor if the DATA input is a logic "0".

When the STROBE is in the logic "0" state, the terminator performs the latch functions, i.e., it follows the changing states of the bus. If the bus goes into the high-Z state or into a power-down condition, the latched terminator retains the data ("1" or "0") that the bus carried before it switched to the high-Z or power-down state. If and when the bus changes from the high-Z state to the state opposite to that which the latch is storing, the bus will override the latch and the terminator will reflect the state on the bus. The small geometries chosen for the inverters in the latch allow this override mode. When checking the data bus whose last state is being preserved by the terminator, a resistor should be used in series with the probe whose input capacitance could trip the small latches. The resistance should be in excess of the output impedance of the latch, i.e., R should be > 30 K at VDD = 10 V.

The STROBE and DATA inputs in each section can be paralleled allowing this device to be used as an 8-bit bus terminator.

The CD40117B types are supplied in 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

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Type Title Date
* Data sheet CD40117B TYPES datasheet (Rev. C) 21 Aug 2003
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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PDIP (N) 14 View options

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