CD74AC574

ACTIVE

Octal Non-Inverting D-Type Flip-Flops with 3-State Outputs

Top

Product details

Parameters

Technology Family AC Input type Standard CMOS Output type 3-State VCC (Min) (V) 1.5 VCC (Max) (V) 5.5 Channels (#) 8 Clock Frequency (Max) (MHz) 125 ICC (uA) 160 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Rating Catalog open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other D-type flip-flop

Features

  • Buffered inputs
  • Typical propagation delay:
    6.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ±24-mA output drive current
    -Fanout to 15 FAST* ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

*FAST is a Registered Trademark of Fairchild Semiconductor Corp.

open-in-new Find other D-type flip-flop

Description

The RCA-CD54/74AC564 and CD54/74AC574 and the CD54/74ACT564 and CD54/74ACT574 octal D-type, 3-state, positive-edge-triggered flip-flops use the RCA ADVANCED CMOS technology. The eight flip-flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE\) controls the 3-state outputs and is independent of the register operation. When the Output Enable (OE\) is HIGH, the outpus are in the high-impendance state. The CD54/74AC/ACT564 and CD54/74AC/ACT574 share the same pin configurations; the CD54/74AC/ACT564, however, has inverted outputs and the CD54/74AC/ACT574 has non-inverted outputs.

The CD74AC/ACT564 and CD74AC/ACT574 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic pakcages (M suffix). Both package types are operable over the following temperature range: Commercial (0- to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT564 and CD54AC/ACT574, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

open-in-new Find other D-type flip-flop
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 15
Type Title Date
* Datasheet Octal D-Type Flip-Flop, 3-State datasheet Dec. 03, 1998
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos