The HC259 and HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.
This latches three active modes and one reset mode. When both the Latch Enable (LE\) and Master Reset (MR\) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latchs output to follow the data input; all other latches are unaffected. The Reset mode (all outputs low) results when LE\ is high and MR\ is low.
Data sheet acquired from Harris Semiconductor
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Bits (#)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Operating temperature range (C)|
||HC||2||6||8||6||28||0.08||28||5.2||-5.2||No||-55 to 125|
|CD54HC259||Samples not available||HC||2||6||8||6||28||0.08||28||5.2||-5.2||No||-55 to 125|