300-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider


Product details


Function Clock generator, Spread-spectrum clock generator Number of outputs 6 Output frequency (Max) (MHz) 300 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type XTAL, Differential, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 85 Features Integrated EEPROM, Pin programmable, SMBus, Spread-spectrum clocking (SSC) Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Clock generators


  • High Performance 3:6 PLL Based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 200 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 300 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Industrial Temperature Range -40°C to 85°C
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

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The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE706 is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27-MHz).

The CDCE706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or re-programmed by in-system programming. A different device setting is programmed via the serial SMBus Interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE706 has three power supply pins, VCC, VCCOUT1, and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE706 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet (Rev. I) Feb. 07, 2008
Application note High Speed Layout Guidelines (Rev. A) Aug. 08, 2017
Technical article How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical article Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) Nov. 22, 2010
Application note Troubleshooting I2C Bus Protocol Oct. 19, 2009
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual Dec. 09, 2008
Application note CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) Nov. 28, 2007
User guide CDCE906/CDCE706 Programming EVM (Rev. B) Aug. 14, 2007
User guide CDCE906/CDCE706 Performance EVM (Rev. B) Apr. 17, 2007
Application note Clock Recommendations for the DM643x EVM Nov. 29, 2006
Application note Recommended Terminations for the Differential Inputs of CDCE906/CDCE706 Aug. 10, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

CDCE906 and CDCE706 EVM
document-generic User guide
document-generic User guide

Software development

SCAC097A.ZIP (14050 KB)
Linux Driver for CDCE706
CDCE706SW-LINUX The Linux driver supports the CDCE706 Programmable 3-PLL Clock Synthesizer / Multiplier / Divider. The Linux driver supports communication through the I2C bus.
Linux Mainline Status

Available in Linux Main line: Yes
Available through N/A

Supported Devices:
  • cdce706
Linux Source Files

The files (...)

SCAC073F.ZIP (88940 KB)
ClockPro™ Programming Software
CLOCKPRO TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:
  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

  • Easy and fast device programming through EEPROM, I2C
  • Based on Labview

Design tools & simulation

SCAC072A.ZIP (119 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SCAC074.ZIP (963 KB)
SCAC075.ZIP (847 KB)

CAD/CAE symbols

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TSSOP (PW) 20 View options

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