The DRV8343-Q1 device is an integrated gate driver for three-phase
applications. The device provides three half-bridge gate drivers, each capable of driving high-side
and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent
MOSFET control for solenoid application. The DRV8343-Q1 generates the correct
gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a
linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate
drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single
power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.
The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to
controller circuits. The configuration settings for the gate driver and device are highly
configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1
device integrates three low-side current sense amplifiers that allow bidirectional current sensing
on all three phases of the drive stage.
A low-power sleep mode is provided to achieve low quiescent current. Internal protection
functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET
short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault
conditions are indicated on the nFAULT pin with details through the device registers for the SPI
device variant.
The DRV8343-Q1 device is an integrated gate driver for three-phase
applications. The device provides three half-bridge gate drivers, each capable of driving high-side
and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent
MOSFET control for solenoid application. The DRV8343-Q1 generates the correct
gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a
linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate
drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single
power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.
The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to
controller circuits. The configuration settings for the gate driver and device are highly
configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1
device integrates three low-side current sense amplifiers that allow bidirectional current sensing
on all three phases of the drive stage.
A low-power sleep mode is provided to achieve low quiescent current. Internal protection
functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET
short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault
conditions are indicated on the nFAULT pin with details through the device registers for the SPI
device variant.