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Product details

Parameters

Function Transmitter Color depth (bpp) 24 Pixel clock frequency (Min) (MHz) 18 Pixel clock frequency (Max) (MHz) 68 Input compatibility LVCMOS, LVTTL Output compatibility FPD-Link LVDS Features No Special Start-Up Sequence Required Between Clock/Data and /PD Pins, Input Clock Detection, Power-down mode, Supports VGA, SVGA, XGA, and Dual Pixel SXGA, PLL Requires No External Components Signal conditioning LVDS Output EMI reduction LVDS, SSC Compatible Diagnostics Throughput (Mbps) 1800 Operating temperature range (C) -10 to 70 open-in-new Find other Display SerDes

Package | Pins | Size

TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Display SerDes

Features

  • No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
  • "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
  • 18 to 68 MHz shift clock support
  • Best-in-Class Setup and Hold Times on TxINPUTs
  • Tx power consumption < 130 mW (typ) at 65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-down mode < 60μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow bus reduces cable size and cost
  • Up to 1.8 Gbps throughput
  • Up to 227 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compatible with TIA/EIA-644 LVDS standard
  • Low profile 56-lead TSSOP package
  • Improved replacement for:
    • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

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Description

The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 9
Type Title Date
* Datasheet DS90C383B 3.3V Prog LVDS Trans 24-Bit FPD Link-65 MHz datasheet (Rev. G) Apr. 17, 2013
Technical articles How to choose a power supply for an automotive camera module Sep. 17, 2020
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov. 09, 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) Jun. 29, 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) Aug. 08, 2017
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices Jan. 13, 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map May 15, 2004
Application note AN-1056 STN Application Using FPD-Link May 14, 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines May 14, 2004

Design & development

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Reference designs

REFERENCE DESIGNS Download
Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment
TIDA-01051 — The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as (...)
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TSSOP (DGG) 56 View options

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