The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) | 05 Mar 2013 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 09 Nov 2018 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 13 Jan 2016 | ||
| Application note | Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) | 26 Apr 2013 | ||
| Design guide | Channel Link I Design Guide | 29 Mar 2007 | ||
| Application note | Multi-Drop Channel-Link Operation | 04 Oct 2004 | ||
| Application note | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 05 Oct 1998 |
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