Product details

Operating temperature range (C) -10 to 70
Operating temperature range (C) -10 to 70
TSSOP (DGG) 56 113 mm² 14 x 8.1
  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • 2.5 / 0 ns Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.38 Gbps Throughput
  • Up to 297.5 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • 2.5 / 0 ns Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.38 Gbps Throughput
  • Up to 297.5 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 8
Type Title Date
* Data sheet DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) 05 Mar 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 Jan 2016
Application note Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) 26 Apr 2013
User guide 28-Bit Channel Link SerDes Evaluation Board 20-85MHz User Guide 25 Jan 2012
Design guide Channel Link I Design Guide 29 Mar 2007
Application note Multi-Drop Channel-Link Operation 04 Oct 2004
Application note CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

FLINK3V8BT-85 — Evaluation kit for FPD-Link family of serializer and deserializer LVDS devices

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

In stock
Limit: 2
Simulation model

DS90CR287 IBIS Model

SNLM210.ZIP (6 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Package Pins Download
NFBGA (NZC) 64 View options
TSSOP (DGG) 56 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos