Product details


Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal LVDS, LVPECL, LVCMOS, LVTTL Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 WSON (NGK) 8 9 mm² 3 x 3 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

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The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet DS90LV001 800 Mbps LVDS Buffer datasheet (Rev. E) Apr. 22, 2013
Application notes How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver Jan. 09, 2019
User guides 3.3V LVDS-LVDS Buffer Evaluation Board User Guide Jan. 27, 2012
Application notes Signaling Rate vs. Distance for Differential Buffers Jan. 26, 2010
White papers Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches Aug. 01, 2001
Application notes An Overview of LVDS Technology Oct. 05, 1998

Design & development

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Design tools & simulation

SNLM045.ZIP (29 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
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SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
WSON (NGK) 8 View options

Ordering & quality

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