4-Channel 800 Mbps LVDS Buffer/Repeater
Product details
Parameters
Package | Pins | Size
Features
- 800 Mbps Data Rate per Channel
- Low Output Skew and Jitter
- LVDS/CML/LVPECL Compatible Input, LVDS Output
- On-Chip 100Ω Input and Output Termination
- 12 kV ESD Protection on LVDS Outputs
- Single 3.3V Supply
- Very Low Power Consumption
- Industrial -40 to +85°C Temperature Range
- Small WQFN Package Footprint
All trademarks are the property of their respective owners.
Description
The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.
In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.
The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.
An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.
The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater datasheet (Rev. L) | May 16, 2013 |
Application note | Signaling Rate vs. Distance for Differential Buffers | Jan. 26, 2010 | |
White paper | Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches | Aug. 01, 2001 | |
Application note | An Overview of LVDS Technology | Oct. 05, 1998 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
WQFN (RTV) | 32 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.