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SN54AHCT573

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Octal Transparent D-type Latches With 3-State Outputs

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Data sheet

SN54AHCT573

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family AHCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (Max) (MHz) 110 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Supply current (Max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns), Flow-through pinout
Number of channels 8 Technology family AHCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (Max) (MHz) 110 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Supply current (Max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns), Flow-through pinout
CDIP (J) 20 167 mm² 26.92 x 7.62 CFP (W) 20 91 mm² 13 x 7
  • Inputs are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Inputs are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SNx4AHCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

The SNx4AHCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
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SN54ACT573 ACTIVE Octal D-type Transparent Latches With 3-State Outputs Shorter avg. propogation delay (8ns), higher avg. drive strength (24mA)

Technical documentation

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Type Title Date
* Data sheet SNx4AHCT573 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. O) PDF | HTML 05 Aug 2014
* SMD SN54AHCT573 SMD 5962-96855 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

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