SN54LS595

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8-Bit Shift Registers With Output Latches

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Product details

Parameters

Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 35 ICC @ nom voltage (Max) (mA) 65 Propagation delay (Max) (ns) 25 IOL (Max) (mA) 24 IOH (Max) (mA) -2.6 3-state output Yes Rating Military Operating temperature range (C) -55 to 125 open-in-new Find other Shift register

Package | Pins | Size

CDIP (J) 16 CFP (W) 16 open-in-new Find other Shift register

Features

  • 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
  • Choice of 3-State ('LS595) or Open-Collector ('LS596) Parallel Outputs
  • Shift Register Has Direct Clear
  • Accurate Shift Frequency:DC to 20 MHz

 

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Description

These devices each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.

Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.

 

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Technical documentation

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Type Title Date
* Data sheet 8-Bit Shift Registers With Output Latches datasheet Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
SMD SN54LS595 SMD 5962-86717 Jun. 21, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
CFP (W) 16 View options

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