Technology FamilyLSVCC (Min) (V)4.75VCC (Max) (V)5.25Voltage (Nom) (V)5F @ nom voltage (Max) (MHz)35ICC @ nom voltage (Max) (mA)65Propagation delay (Max) (ns)25IOL (Max) (mA)24IOH (Max) (mA)-2.63-state outputYesRatingMilitaryOperating temperature range (C)-55 to 125open-in-newFind other Shift register
These devices each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.