Product details


Protocols LVDS, MIPI DSI Speed (Max) (Gbps) 4 Supply voltage (V) 1.8 Operating temperature range (C) -40 to 85 open-in-new Find other HDMI, DisplayPort & MIPI ICs

Package | Pins | Size

NFBGA (ZXH) 64 25 mm² 5 x 5 open-in-new Find other HDMI, DisplayPort & MIPI ICs


  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
  • FlatLink™ output for single-link LVDS
  • Supports single channel DSI to single-link LVDS operating mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

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The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet SN65DSI83 MIPI DSI Bridge to FLAT LINK LVDS Single Channel DSI to SL LVDS Bridge datasheet (Rev. I) Oct. 01, 2020
* User guide HSSC MicroStar BGA Discontinued and Redesigned Jan. 18, 2021
Application note Troubleshooting SN65DSI8x - Tips and Tricks Aug. 27, 2018
User guide SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide Nov. 17, 2015
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) Apr. 11, 2013
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) Apr. 08, 2013
Technical article Live from CES 2013 - Mobile tablet interface Jan. 10, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
The SN65DSI83EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implement the SN65DSI85 device in system hardware.  This EVM can be used as a hardware reference design for any implementation using the SN65DSI83 device. This EVM includes (...)
  • Plug and play design
  • Two input options for DSI video signal (QSH type connector and FX type connector)
  • Two output port options available for the LVDS output signals (QSH type connector and I-PEX type connector)
  • I2C interface to configure internal registers
  • LED backlight driver circuitry using TI's (...)

Software development

Tuner video configuration software tool
DSI-TUNER The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)
  • Generates the video timing and the configuration
    register values required to transfer the DSI data to the LVDS panel
  • Calculates timing and register values based on
    inputs entered in tool

Design tools & simulation

SLLJ007.ZIP (1092 KB) - HSpice Model
SLLM202.ZIP (254 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
NFBGA (ZXH) 64 View options

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