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SN65DSI86

ACTIVE

Dual-channel MIPI® DSI to embedded DisplayPort™ (eDP ) bridge

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Data sheet

SN65DSI86

ACTIVE
Data sheet Order now

Product details

Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbpp) 12 Operating temperature range (°C) -40 to 85
Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbpp) 12 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² (5 mm × 5 mm)
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
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Technical documentation

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* Data sheet SN65DSI86 MIPI DSI to eDP Bridge datasheet (Rev. C) PDF | HTML Oct 1, 2020
Application brief SN65DSI86 Programming Guide Aug 17, 2018
Application note SN65DSI86 and SN65DSI96 Hardware Implementation Guide Oct 8, 2013

Design & development

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Evaluation board

SN65DSI86EVM — MIPI® DSI bridge to eDP evaluation module

The SN65DSI86EVM evaluation module (EVM) is a printed-circuit board (PCB) to help you evaluate the SN65DSI86 device for video applications with DSI and DisplayPort interface. This EVM can also be used as a hardware reference design for any implementation of the SN65DSI86.

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IDE, configuration, compiler or debugger

DSI-TUNER — Tuner video configuration software tool

The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)

Supported products & hardware
Simulation model

SN65DSI86 IBIS Model (Rev. A)

SLLM226A.ZIP (92 KB) - IBIS model
Supported products & hardware
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NFBGA (ZXH) 64 Ultra Librarian
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