Top

Product details

Parameters

Function Repeater, Translator Protocols LVDS, LVPECL, CML Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2000 Input signal CML, LVDS, LVPECL Output signal LVPECL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP
open-in-new Find other LVDS, M-LVDS & PECL ICs

Description

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

open-in-new Find other LVDS, M-LVDS & PECL ICs
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet SN65LVDx10x Differential Translator/Repeater datasheet (Rev. E) Jul. 20, 2015
Application note Signaling Rate vs. Distance for Differential Buffers Jan. 26, 2010
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007
Application note DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Feb. 19, 2003
User guide 2-GBPS Differential Repeater EVM (Rev. A) Nov. 11, 2002
More literature HPL EVM Program Aug. 29, 2002
User guide 2-GBPS Differential Repeater EVM Aug. 08, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
99
Description

The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to 50-ohm (...)

Features

Hardware: SN65LVDS100/101EVM or SN65CML100EVM PWB

  • Screw-type SMA jacks serve as the I/O connectors
  • Banana jacks serve as the DC power input terminals
EVALUATION BOARD Download
99
Description

The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to 50-ohm (...)

Features

Hardware: SN65LVDS100/101EVM or SN65CML100EVM PWB

  • Screw-type SMA jacks serve as the I/O connectors
  • Banana jacks serve as the DC power input terminals

Literature:

a) The SN65LVDS100/101EVM or SN65CML100EVM user's guide (SLLU040A) Includes:

  • schematic
  • board layout
  • test results

b) The SN65LVDS100/101 data sheet (...)

Design tools & simulation

SIMULATION MODEL Download
SLLC125A.ZIP (6 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

Reference designs

REFERENCE DESIGNS Download
Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications
TIDA-01378 — This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos