TIDA-01378
Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications
TIDA-01378
Overview
This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver applications specified for cable modem termination systems (CMTS) and supports up to 196 MHz of upstream signal bandwidth. The circuit solves the filtering and analog signal processing requirements for the DOCSIS 3.1 standard, which makes it easier for system designers to readily incorporate the design on the CMTS-side of the upstream signal path.
Features
- AC-coupled signal path from 100 kHz to 204 MHz with 196 MHz of upstream-signal-bandwidth support for DOCSIS 3.1 applications
- 58 dBFs of minimum system SNR (200 MHz BW) for –1-dBFs input at the ADC
- 70 dBFs of minimum system SFDR for –1-dBFs input at the ADC
- 1.71 A of average active-state current consumption on 5-V nominal wall mount power supply
- Output data rate of four lanes per ADC at 5.0 Gbps with JESD204B interface subclass-1 support
Communications equipment
Personal electronics
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUCG9.PDF (648 K)
Reference design overview and verified performance test data
TIDRPN2.PDF (139 K)
Detailed schematic diagram for design layout and components
TIDRPN3.PDF (301 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRPN4.ZIP (2005 K)
Detailed overview of design layout for component placement
TIDRPN6.ZIP (444 K)
Files used for 3D models or 2D drawings of IC components
TIDCD46.ZIP (3337 K)
Design file that contains information on physical board layer of design PCB
TIDRPN5.PDF (2660 K)
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
Buck converters (integrated switch)
TPS54319 — 2.95 V to 6 V input, 3 A, 2 MHz SWIFT™ synchronous step-down converter in a 3 mm x 3 mm QFN package
Data sheetClock jitter cleaners & synchronizers
LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
Data sheetHigh-speed ADCs (>10MSPS)
ADS54J40 — Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)
Data sheetLVDS, M-LVDS & PECL ICs
SN65LVDS101 — 2-Gbps LVDS, LVPECL & CML to LVPECL repeater/translator
Data sheetLVDS, M-LVDS & PECL ICs
SN65LVDS4 — 500-Mbps LVDS single high-speed transceiver
Data sheetLinear & low-dropout (LDO) regulators
TPS735 — 500-mA, low-IQ, low-dropout voltage regulator with enable
Data sheetLinear & low-dropout (LDO) regulators
TPS7A47 — 1-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable
Data sheetLinear & low-dropout (LDO) regulators
TPS7A8101 — 1-A, high-PSRR, adjustable ultra-low-dropout voltage regulator with enable
Data sheetN-channel MOSFETs
CSD17313Q2 — 30-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 32 mOhm
Data sheetRF VGAs
LMH2832 — Fully-Differential, Dual, 1.1 GHz Digital Variable Gain Amplifier
Data sheeteFuses & hot swap controllers
TPS2400 — 5.5-V over voltage protection controller with 100-V input transient protection
Data sheetStart development
Technical documentation
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| Type | Title | Date | |
|---|---|---|---|
| * | Design guide | Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications | Oct. 26, 2016 |
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