Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications
TIDA-01378
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Key Document
Description
This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver applications specified for cable modem termination systems (CMTS) and supports up to 196 MHz of upstream signal bandwidth. The circuit solves the filtering and analog signal processing requirements for the DOCSIS 3.1 standard, which makes it easier for system designers to readily incorporate the design on the CMTS-side of the upstream signal path.
Features
- AC-coupled signal path from 100 kHz to 204 MHz with 196 MHz of upstream-signal-bandwidth support for DOCSIS 3.1 applications
- 58 dBFs of minimum system SNR (200 MHz BW) for –1-dBFs input at the ADC
- 70 dBFs of minimum system SFDR for –1-dBFs input at the ADC
- 1.71 A of average active-state current consumption on 5-V nominal wall mount power supply
- Output data rate of four lanes per ADC at 5.0 Gbps with JESD204B interface subclass-1 support
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Schematic/Block Diagram
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Test Data
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TI Devices (11)
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| Sample & Buy |
Design Kits & Evaluation Modules |
| ADS54J40 |
Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC) |
Analog-to-digital converters (ADCs) |
Sample & Buy |
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| CSD17313Q2 |
30-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 32 mOhm |
MOSFETs |
Sample & Buy |
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| LMH2832 |
Fully-Differential, Dual, 1.1 GHz Digital Variable Gain Amplifier |
RF amplifiers |
Sample & Buy |
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| LMK04828 |
Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. |
Clocks & timing |
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| SN65LVDS101 |
2-Gbps LVDS, LVPECL & CML to LVPECL repeater/translator |
Interface |
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| SN65LVDS4 |
500-Mbps LVDS single high-speed transceiver |
Interface |
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| TPS2400 |
5.5-V over voltage protection controller with 100-V input transient protection |
Power switches |
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| TPS54319 |
2.95 V to 6 V input, 3 A, 2 MHz SWIFT™ synchronous step-down converter in a 3 mm x 3 mm QFN package |
Step-down (buck) regulators |
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| TPS735 |
500-mA, low-IQ, low-dropout voltage regulator with enable |
Power management |
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| TPS7A47 |
1-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable |
Power management |
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| TPS7A8101 |
1-A, high-PSRR, adjustable ultra-low-dropout voltage regulator with enable |
Power management |
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CAD/CAE symbols
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Texas Instruments and Accelerated Designs, Inc. have collaborated together to provide TI customers with schematic symbols and PCB layout footprints for TI products.
Step 1: Download and install the free download.
Step 2: Download the Symbol and Footprint from the CAD.bxl file table.
Step 3: Open the .bxl file with the Ultra Librarian software.
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Technical documentation
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User guide (3)
| | PDF | 648 |
26 Oct 2016
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| | PDF | 2471 |
12 Jan 2016
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| | PDF | 2141 |
27 Jan 2012
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Design files (6)
| | ZIP | 3337 |
30 Jan 2017
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| | ZIP | 444 |
30 Jan 2017
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| | PDF | 2660 |
30 Jan 2017
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| | ZIP | 2005 |
30 Jan 2017
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| | PDF | 301 |
30 Jan 2017
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| | PDF | 139 |
30 Jan 2017
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