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Dual LVDS receiver

SN65LVDS9637

ACTIVE

Product details

Parameters

Function Receiver Protocols LVDS Number of Tx 0 Number of Rx 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 150 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

HVSSOP (DGN) 8 15 mm² 3 x 4.9 SOIC (D) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 3.91 x 4.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Meet or Exceed the Requirements of ANSI
    TIA/EIA-644 Standard
  • Operate With a Single 3.3-V Supply
  • Designed for Signaling Rates of up to
    150 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Typical Propagation Delay Time of 2.1 ns
  • Power Dissipation 60 mW Typical Per
    Receiver at Maximum Data Rate
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Output
    Levels
  • Pin Compatible With AM26LS32, MC3486,
    and µA9637
  • Open-Circuit Fail-Safe
  • Cold Sparing for Space and High-Reliability
    Applications Requiring Redundancy
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Description

The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to 85°C. The SN55LVDS32 device is characterized for operation from –55°C to 125°C.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers datasheet (Rev. R) Aug. 06, 2014
Application notes LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application notes How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application notes How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SLLC018.ZIP (4 KB) - IBIS Model
SIMULATION TOOLS Download
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
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  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
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SIMULATION TOOLS Download
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TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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CAD/CAE symbols

Package Pins Download
HVSSOP (DGN) 8 View options
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

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