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1500-Mbps LVDS dial high speed differential driver

SN65LVDS9638

ACTIVE

Product details

Parameters

Function Driver Protocols LVDS Number of transmitters 2 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVTTL Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

HVSSOP (DGN) 8 9 mm² 3 x 3 SOIC (D) 8 19 mm² 3.91 x 4.9 SOIC (D) 8 19 mm² 4.9 x 3.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load
  • Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps)
  • Typical Propagation Delay Times of 1.7 ns
  • Operate From a Single 3.3-V Supply
  • Power Dissipation 25 mW Typical Per Driver at 200 MHz
  • Driver at High-Impedance When Disabled or With VCC = 0
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels
  • Pin Compatible With AM26LS31, MC3487, and µA9638
  • Cold Sparing for Space and High-Reliability Applications Requiring Redundancy

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Description

The SN55LVDS31, SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 devices are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

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Technical documentation

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Type Title Date
* Data sheet SNx5LVDSxx High-Speed Differential Line Drivers datasheet (Rev. N) Jan. 21, 2021
Application note LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application note How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application note How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018

Design & development

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Design tools & simulation

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CAD/CAE symbols

Package Pins Download
HVSSOP (DGN) 8 View options
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

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