SN7405

ACTIVE

Hex inverters with open collector outputs

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Product details

Parameters

Technology Family TTL VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 6 IOL (Max) (mA) 16 IOH (Max) (mA) 0 ICC (Max) (uA) 33 Input type Bipolar Output type Open-Collector Features High speed (tpd 10-50ns) Data rate (Mbps) 70 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 open-in-new Find other Inverting buffer/driver

Features

  • Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
  • Dependable Texas Instruments Quality and Reliability

The SN5405 is obsolete and no longer is supplied.

open-in-new Find other Inverting buffer/driver

Description

These devices contain six independent inverters. To perform correctly, the open-collector outputs require pullup resistors. These devices may be connected to other open-collector outputs to implement active-low wired-OR or active-high wire-AND functions. Open-collector devices often are used to generate high VOH levels.

open-in-new Find other Inverting buffer/driver
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54LS05, SN54S05, SN7405, SN74LS05, SN74S05 datasheet (Rev. A) Nov. 03, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDLM072.ZIP (6 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options

Ordering & quality

Support & training

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