Product details

Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 67 Features Programmable Flags, Unidirectional
Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 67 Features Programmable Flags, Unidirectional
SSOP (DL) 56 191 mm² 18.42 x 10.35
  • Member of the Texas Instruments WidebusTM Family
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Input-Ready Flag Synchronized to Write Clock
  • Output-Ready Flag Synchronized to Read Clock
  • 64 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
  • Bidirectional Configuration and Width Expansion Without Additional Logic
  • Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 67 MHz
  • Pin-to-Pin Compatible With SN74ACT7803 and SN74ACT7805
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus and OEC are trademarks of Texas Instruments Incorporated.

  • Member of the Texas Instruments WidebusTM Family
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
  • Read and Write Operations Synchronized to Independent System Clocks
  • Input-Ready Flag Synchronized to Write Clock
  • Output-Ready Flag Synchronized to Read Clock
  • 64 Words by 18 Bits
  • Low-Power Advanced CMOS Technology
  • Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
  • Bidirectional Configuration and Width Expansion Without Additional Logic
  • Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
  • Data Rates up to 67 MHz
  • Pin-to-Pin Compatible With SN74ACT7803 and SN74ACT7805
  • Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing

    Widebus and OEC are trademarks of Texas Instruments Incorporated.

The SN74ACT7813 is a 64-word × 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

The SN74ACT7813 is a 64-word × 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet 64 X 18 Clocked First-In, First-Out Memory datasheet (Rev. B) 01 Apr 1998
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996
Application note FIFO Memories: Solutions For Increasing Clock Rates And Data Widths (Rev. A) 01 Mar 1996
Application note Power-Dissipation Calculations for TI FIFO Products (Rev. A) 01 Mar 1996

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