SN74AHCT74

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

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Product details

Parameters

Channels (#) 2 Technology Family AHCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 70 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns) open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other D-type flip-flop

Features

  • Inputs Are TTL-Voltage Compatible
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

open-in-new Find other D-type flip-flop

Description

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

open-in-new Find other D-type flip-flop
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 22
Type Title Date
* Datasheet SN54AHCT74, SN74AHCT74 datasheet (Rev. O) Jun. 27, 2013
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCLM075.ZIP (22 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
High Efficiency 100W Active Clamp Forward 220V-400VDC Input, 28V/ 3.6A Reference Design
PMP7453 This reference design generates an isolated 28V/100W output from a high voltage DC input. This design is intended to operate from the output of PFC front end regulator. The UCC2897A is used to control an active clamp forward converter. Self-driven synchronous rectifiers allow for over 92 (...)
document-generic Schematic
REFERENCE DESIGNS Download
220V-400VDC Input, 12V/100W Active Clamp Forward Reference Design
PMP6961 This reference design generates an isolated 12V/100W output from a high voltage DC input. This design is intended to operate from the output of a PFC front end regulator. The UCC2897A is used to control an active clamp forward converter. Self-driven synchronous rectifiers allow for over 91 (...)
document-generic Schematic
REFERENCE DESIGNS Download
220V-400VDC Input, 5V/100W Active Clamp Forward Reference Design
PMP7413 This reference design generates an isolated 5V/100W output from a high voltage DC input. This design is intended to operate from the output of a PFC front end regulator. The UCC2897A is used to control an active clamp forward converter. Self-driven synchronous rectifiers allow for 91% efficiency. An (...)
document-generic Schematic
REFERENCE DESIGNS Download
220V-400VDC Input, 12V/160W Active Clamp Forward
PMP7410 — This reference design generates an isolated 12V/160W output from a high voltage DC input. This design is intended to operate from the output of PFC front end regulator. The UCC2897A is used to control an active clamp forward converter. Texas Instruments CSD18531Q5A synchronous rectifiers allow this (...)

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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